SRAM Configuration Cell for Low-Power Field Programmable Gate Arrays

ABSTRACT

A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.

BACKGROUND

The present invention relates to user-programmable integrated circuitssuch as field programmable gate array integrated circuits. Moreparticularly, the present invention relates to static random-accessmemory configuration cells for use in user-programmable integratedcircuit devices such as field programmable gate array (FPGA) integratedcircuits.

FIG. 1 shows a prior-art 6-transistor static random-access memory (SRAM)cell driving the gate of an n-channel switch transistor for use in auser-programmable integrated circuit such as an FPGA. The SRAM cellincludes a first p-channel transistor in series with a first n-channeltransistor between V_(DD) and ground. The gates of the first p-channeltransistor and the first n-channel transistor are connected together.The drains of the first p-channel transistor and the first n-channeltransistor are connected together to define a first output node Y.

A second p-channel transistor is connected in series with a secondn-channel transistor between V_(DD) and ground, having their gatesconnected together. The drains of the second p-channel transistor andthe second n-channel transistor are connected together to define asecond output node Y!. The gates of the first p-channel and re -channeltransistor are connected to the second output node Y! and the gates ofthe second p-channel and n-channel transistors are connected to thefirst output node Y. The type of memory cell depicted in FIG. 1 issometimes referred to in the art as a cross-coupled memory cell.

The first node Y is coupled to a first bitline BL! associated with thememory cell through an n-channel transistor having its gate connected toa wordline WL associated with the memory cell. The second node Y! iscoupled to a second bitline BL associated with the memory cell throughan n-channel transistor having its gate connected to the wordline WLassociated with the memory cell. The first and second bitlines BL!, BLare complementary.

The n-channel switch transistor switch has its gate connected to thesecond node Y! and is used to selectively connect one signal to anotherin the programmable routing of the FPGA, as controlled by the state ofthe SRAM cell. The transistors in the 6-transistor SRAM memory cell ofFIG. 1 are all ordinary low-voltage transistors. The supply voltage isthe normal logic supply voltage V_(DD).

There are a few drawbacks to the use of the memory cell of FIG. 1.First, the n -channel switch transistor cannot pass a full V_(DD)voltage, but only V_(DD) less a voltage V_(t), where V_(t) is thethreshold voltage of the n-channel switch transistor.

The n-channel switch transistor must have a relatively low V_(t) inorder to provide good speed. An undersirable consequence of using atransistor having a low V_(t) is that the n-channel switch transistorwill leak current from its source to drain terminals even when its gateis at ground and the device is shut off This unnecessarily contributesto the static power consumption of the FPGA.

One solution to these problems is to supply the SRAM cell with a voltageV_(OD) selected to be higher than V_(DD) so that the gate of the switchis over-driven to a voltage above V_(DD). To withstand the highervoltage, the planar transistor devices used in the SRAM cell are madehaving both a thicker gate oxide layer to provide a higher maximumV_(GS) breakdown voltage for the higher gate voltages being encountered,and a longer channel to prevent punch-through at the higher drain tosource voltages being encountered. The n-channel planar switchtransistor driven by the SRAM cell uses a thicker oxide to withstand thevoltages to which its gate will be subjected but still has the ordinarychannel length because it is a low-voltage device. This solution to theprior art problem is described in Telikepalli, “Power vs. Performance:The 90 nm Inflection Point,” Xilinx White Paper, 2006. This document isfound at https://www.xilinx/com/support/documentation/whitepapers/wp223.pdf. As disclosed in Telikepalli, the gate oxide layer usedin the switch transistor is thicker than the gate oxide layer used inthe standard logic devices but still thinner than the gate oxide used instandard I/O devices, in order not to impact switching speed, meaningthat it must be formed using an additional oxide formation step notpresent in the standard process flow.

This arrangement disclosed in Telikepalli addresses the three issuesmentioned above, but introduces new problems. First, the long channeldevices in the SRAM cell takes up extra die area on the integratedcircuit. In addition, the need to provide a device having an additionalmedium-thickness oxide for the SRAM cell complicates the manufacturingprocess. As technology has advanced to feature sizes below 40 nm, andtransistor geometry has evolved from planar geometry to FinFET geometry,it is no longer feasible to provide such non-standard medium thicknessoxide devices. A reason for this is the advent of high-k gate processessuch as the ones described inhttps://www.eecg.toronto.edu/˜charlesc/chiasson fpl2013.pdf. Below 20nm, when process technology changes from planar to FinFET transistors,it becomes even more difficult to continue to support a specialnon-standard medium-thickness oxide. As a result, at 20 nm FPGAmanufacturers have started using CMOS transmission gates as switches.These do not require overdriving the gates to pass a full V_(DD).

FIG. 2 shows a prior-art 6-transistor static random-access memory (SRAM)cell identical to the SRAM memory cell shown in FIG. 1 driving the gatesof an n-channel transistor switch and a p-channel transistor connectedtogether to form a conventional CMOS transmission gate, also known as apass-gate, for use in a user-programmable integrated circuit such as anFPGA. As in the SRAM memory cell of FIG. 1, the transistors are allordinary low-voltage transistors. The use of a complementary pair of n-channel and p-channel transistors as the switch solves the problem ofnot passing a full V_(DD) voltage. However, because a pair of devicesinstead of a single device is used, the area of the switch is increased,and the leakage is not improved. Furthermore, the need to bring both thetrue (Y) and complement (Y!) outputs of the SRAM cell to the switchdevices requires a significant increase in layout area due to additionalmetal layer wiring requirements.

For a discussion of the tradeoffs of using pass-gates in FPGAs, see:http://www.eecg.toronto.edu/˜charlesc/chiasson fpl2013.pdf

In summary, it would be very desirable to find a way to continue to useNMOS switches with overdriven gates but without making the processtechnology more complex and without increasing the area of the SRAM celltoo much.

BRIEF DESCRIPTION

According to one aspect of the present invention, a random-access memorycell includes first and second voltage supply nodes, first and secondcomplementary output nodes, first and second complementary bit linesassociated with the memory cell, and a word line associated with thememory cell. Pairs of series-connected cross-coupled p -channel andn-channel hybrid FinFET transistors are connected between the voltagesupply nodes, the first bit line coupled to the first output node, andthe second bit line coupled to the second output node.

According to another aspect of the present invention, control circuitrycoupled to the memory cell is configured to supply a programmingpotential to the first voltage supply node during a programming mode andsupply an operating potential higher than the programming potentialduring an operating mode.

According to another aspect of the present invention, a method ofoperating a random-access memory cell formed from pairs ofseries-connected cross-coupled p -channel and n-channel hybrid FinFETtransistors coupled to a pair of complementary bit lines through a pairof hybrid FinFET select transistors includes during a programming modeof operation powering the memory cell with a first voltage potential andplacing one of the first potential and 0V on a first one of the bitlines and the other one of the first potential and 0V on a second one ofthe bit lines, and during a read mode of operation powering the memorycell with a second voltage potential higher than the first voltagepotential and placing about half of the second voltage potential on bothof the complementary bit lines.

According to another aspect of the present invention, an integratedcircuit includes a plurality of first random-access memory cells eachincluding first and second voltage supply nodes, first and secondcomplementary output nodes, first and second complementary bit linesassociated with each first memory cell, and a word line associated witheach first memory cell. Each first memory cell further including pairsof series-connected cross-coupled p-channel and n-channel hybrid FinFETtransistors connected between the voltage supply nodes, the first bitline coupled to the first output node, and the second bit line coupledto the second output node. A plurality of second random-access memorycells each including first and second voltage supply nodes, first andsecond complementary output nodes, first and second complementary bitlines associated with each first memory cell, and a word line associatedwith each first memory cell. Each second memory cell further includingcross-coupled p-channel and n-channel hybrid FinFET transistorsconnected between the voltage supply nodes, the first bit line coupledto the first output node, and the second bit line coupled to the secondoutput node.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The invention will be explained in more detail in the following withreference to embodiments and to the drawing in which are shown:

FIG. 1 is a schematic diagram of a prior-art SRAM memory cell;

FIG. 2 is a schematic diagram of another prior-art SRAM memory cell;

FIG. 3A is a schematic diagram of an SRAM configuration cell inaccordance with one aspect of the present invention;

FIG. 3B is a table listing the potentials applied to the various nodesof the SRAM configuration cell of FIG. 3A in read mode (normal operatingmode), and the two cases of programming mode;

FIG. 4 is a flow diagram showing an illustrative method in accordancewith the present invention;

FIG. 5 is a diagram of an integrated circuit 70 having an illustrativearrangement of different SRAM memory cells in accordance with anotheraspect of the present invention.

DETAILED DESCRIPTION

Persons of ordinary skill in the art will realize that the followingdescription of the present invention is illustrative only and not in anyway limiting. Other embodiments of the invention will readily suggestthemselves to such skilled persons.

Referring now to FIG. 3A, a 10-transistor static random-access memory(SRAM) configuration cell (shown within dashed region 10) driving thegate of an n-channel transistor switch 14 for use in a user-programmableintegrated circuit such as an FPGA is shown. It is to be understand thata configuration cell does not require high speed switching, since thecell is set at initial configuration, and is generally not changedthereafter. The SRAM configuration cell 10 includes a first pair ofseries-connected p -channel FinFET transistors 16 a and 16 b in serieswith a first pair of series-connected re- channel FinFET transistors 18a and 18 b disposed between two voltage supply rails 20 and 22. Thedrains of the second of the first pair of series-connected p-channelFinFET transistors 16 b and the first of the first pair ofseries-connected n-channel FinFET transistors 18 a are connectedtogether to define a first output node Y at reference numeral 24.

A second pair of series-connected p-channel FinFET transistors 26 a and26 b in series with a second pair of series-connected n-channel FinFETtransistors 28 a and 28 b is disposed between the two power rails 20 and22. The drains of the second of the second pair of series-connectedp-channel FinFET transistors 26 b and the first of the second pair ofseries-connected n-channel FinFET transistors 28 a are connectedtogether to define a second output node Y! at reference numeral 30.

The gates of the first pair of series-connected p-channel FinFETtransistors 16 a and 16 b and the first pair of series-connectedn-channel FinFET transistors 18 a and 18 b are connected to the secondoutput node Y! at reference numeral 30. The gates of the second pair ofseries-connected p-channel FinFET transistors 26 a and 26 b and thesecond pair of series-connected n-channel FinFET transistors 28 a and 28b are connected to the first output node Y at reference numeral 24. Likethe memory cell of FIGS. 1 and 2, the arrangement of SRAM configurationcell 10 of FIG. 3 can be referred to as being cross -coupled.

The first output node Y at reference numeral 24 is coupled to a firstbitline 32 (BL!) associated with the SRAM configuration cell 10 throughan n-channel select transistor 34 having its gate connected to awordline (WL) 36 associated with the SRAM configuration cell 10. Thesecond output node Y! at reference numeral 30 is coupled to a secondbitline 38 (BL) associated with the SRAM configuration cell 10 throughan re -channel select transistor 40 having its gate connected to thewordline (WL) 36 associated with the SRAM configuration cell 10. Thefirst and second bitlines BL! (32) and BL (38) are complementary.

The n-channel FinFET transistor switch 14 has its gate connected to thesecond node Y! (30) and is used to selectively connect one signal toanother in the programmable routing of the FPGA, as controlled by thestate of the SRAM configuration cell 10.

The p-channel and n-channel FinFET transistor devices 16 a, 16 b, 18 a,18 b, 26 a, 26 b, 28 a, and 28 b are hybrid FinFET transistor devices.Hybrid FinFET transistor devices, as used herein, share threeattributes: 1) they have the thick gate oxide layers of high-voltageinput/output (I/O) devices; 2) they have the short channel geometries ofordinary low-voltage logic transistor FinFET devices; and 3) they havehigher channel implant doses than the low-voltage FinFET devices inorder to allow them to withstand the higher operating voltages withoutsuffering from punch through. These hybrid FinFET transistor devices aredisclosed in co-pending application Ser. No. 62/594,349, attorney DocketNumber 17-33867, filed on the same date as the instant application andentitled “HYBRID HIGH-VOLTAGE LOW-VOLTAGE FINFET DEVICE”. This co-pending application is incorporated by reference herein in itsentirety, and the term “hybrid FinFET transistors” and “hybrid FinFETtransistor devices” as used herein are intended to refer to the devicesdisclosed in the above-identified co-pending patent application.

The hybrid FinFET transistor devices used in the SRAM configuration cell10 of the present invention can tolerate a voltage greater than V_(DD)on their gates, yet are no larger than an ordinary low-voltage FinFETdevice. Unlike the prior-art FinFET devices, the hybrid FinFET devicesused in the SRAM configuration cell 10 of the present invention do notrequire any additional “medium-thickness” gate oxide layers or otherprocess changes, and as disclosed in the above-identified co-pendingpatent application, they may be fabricated using existing processes withthe addition of only minimal adjustments to the process flow, mostlyinvolving the geometry of the masks used in gate formation and channelimplant steps of the fabrication process. The hybrid FinFET transistordevice is especially suitable for use as a switch in a non-volatilememory user programmable circuit such as an FPGA, where adequateoverdrive voltage is readily available from the non-volatile memoryconfiguration cell.

As disclosed in the above-identified co-pending patent application,hybrid FinFET transistor devices can also be made having p-channelpolarity. The goal is to have an SRAM configuration cell that canprovide sufficient overdrive to use a hybrid switch device, but withoutcomplicating the manufacturing process with additional requirements fornew devices. Furthermore, the SRAM configuration cell should consume aslittle die area as possible.

The first aspect of the invention is to form the SRAM configuration cell10 from the same hybrid FinFET transistor devices used for the switchtransistor 14. This avoids any need for a large spacing between theconfiguration bits and switches. The hybrid devices can withstand theelevated gate voltage due to their thick oxide. However the hybridFinFET transistor devices still cannot withstand the source-drainvoltages encountered in the memory cell itself without undue leakagethat can otherwise inadvertently switch the state of the memory cell.

According to another aspect of the present invention, and as illustratedin the Table of FIG. 3B, exceeding V_(DD) across the source and drain ofthe select transistors 34, 40 in the SRAM configuration cell 10 isavoided. During normal operating conditions (read mode) the memory cell10 is powered by V_(OD), which can be, for example, 1.5V. Duringprogramming (write mode) the voltage powering the memory cell 10 isreduced to V_(DD), for example 0.8V to allow the use of a singletransistor as select transistors 34 and 40. Prior to writing data to theSRAM configuration cell 10, control circuit 42 coupled to power rail 20drops V_(OD) to V_(DD), and then the SRAM configuration cell 10 iswritten to as usual by setting WL 36 and bitlines BL! 32 and BL 38 toappropriate voltages of 0 or V_(DD) as known in the art. To program SRAMconfiguration cell 10 to turn on the hybrid FinFET transistor switch 14,control circuit 42 coupled to power rail 20 sets node 20 to V_(DD), WL36 is set to V_(DD) BL 38 is set to V_(DD) and BL! 32 is set to 0V asshown in the table of FIG. 3B. To program SRAM configuration cell 10 toturn off the hybrid FinFET transistor switch 14, control circuit 42coupled to power rail 20 sets node 20 to V_(DD), WL 36 is set to V_(DD),BL 38 is set to 0V and BL! 32 is set to V_(DD) as also shown in thetable of FIG. 3B.

During a read mode (normal operation) of the SRAM configuration cell 10or other user-programmable circuit designed using the principles setforth herein, control circuit 42 sets the voltage on power rail 18 toV_(OD) to overdrive the gate of switch transistor 14, but the bit lines32 and 38 are maintained at V_(DD)/2 to avoid undue leakage through theselect devices as also shown in the table of FIG. 3B. Configuration andcontrol of circuits such as control circuitry 42 is well known in theart.

This leaves only the remaining FINFET transistors in the SRAMconfiguration cell 10 exposed to source-drain voltages above V_(DD)during normal circuit operation (i.e., read operation). To avoid thisproblem, two transistors 16 a, 16 b, 18 a, 168, 26 a, 26 b, and 28 a, 28b are provided in series in place of a single transistor shown in theprior art SRAM cell of FIG. 1. Thus V_(OD) is divided across twooff-state devices, and neither of the off -state devices sees asource-drain voltage in excess of V_(OD)/2. During operation, with thebit lines at V_(DD)/2, the SRAM configuration cell 10 can be supplied byV_(OD) with no risk of exceeding the limit of any of the hybrid FINFETtransistors 16 a, 16 b, 18 a, 18 b, 26 a, 26 b, 28 a, 28 b.

Referring now to FIG. 4, a flow diagram shows an illustrative method foroperating an array of the memory cells of the present invention. Themethod starts at reference numeral 50.

At reference numeral 52 a command places the array in programming mode.This command is asserted at device powerup as well as at other selectedtimes. At reference numeral 56, in response to the command placing thearray in programming mode the voltage at the first voltage supply nodeis set at the programming voltage V_(DD). At reference numeral 58, amemory cell is selected and is programmed by asserting appropriatevoltage potentials on the word lines and bit lines of the memory array.As indicated by decision diamond 60, cells are selected and programmeduntil all of the memory cells in the array have been programmed.

Next, at reference numeral 64, a command places the array in read mode,sometimes referred to as the “normal operating mode” of the memory cell.In response to the command placing the array in programming mode, thevoltage at the first voltage supply node is set at the programmingvoltage V_(OD). The process ends at reference numeral 66.

Further in accordance with the present invention, user-programmablecircuits such as FPGA circuits also require some configuration bits thatdo not drive switch gates, but instead drive logic inputs, and thus neednot be driven by a voltage in excess of a V_(t) above V_(DD). An examplewould be the 2̂N bits used to configure an N-input LUT. Normallymanufacturers prefer to use the same SRAM configuration cell for allpurposes (including both controlling the switches and configuring thelogic) to simplify the design and manufacturing. However in this contextit is preferable to continue to use the smaller prior-art SRAM cell ofFIG. 1 to drive the logic, and reserve use of the larger SRAMconfiguration cell 10 of FIG. 2 to those cases where it is necessary tooverdrive switch gates.

Persons of ordinary skill in the art will appreciate that, because it isso important to minimize die area, providing two devices in series as inthe SRAM configuration cell 10 is not the sort of thing that wouldtypically be done in an SRAM configuration cell. However, the use of twodifferent types of SRAM cells in the FPGA (the SRAM cell of FIG. 1 wherepossible and the SRAM configuration cell of FIG. 2 where necessary), thearea savings from enabling the use of an NMOS hybrid switch instead of aCMOS switch, and reduction of the supply voltage to V_(DD) during writeoperations to limit the source-drain voltage on the addressing devicesand using pairs of series devices for the remaining devices in the SRAMcell can be acceptable as part of an overall solution for FPGAconfiguration.

This aspect of the invention is shown in FIG. 5, a diagram of anintegrated circuit 70 having an illustrative arrangement of differentSRAM memory cells in accordance with the present invention. SRAM memorycells 72 a, 72 b, 72 c, and 72 d drive inputs to LUT 74. Similarly, SRAMmemory cells 76 a, 76 b, 76 c, and 76 d drive inputs to LUT 78; and SRAMmemory cells 80 a, 80 b, 80 c, and 80 d drive inputs to LUT 82. Theinputs to LUTs 74, 78, and 82 are logic inputs that do not need to beoverdriven. Accordingly, prior-art 6T SRAM cells such as those depictedin FIG. 1 can be employed.

SRAM configuration cell 84 drives n-channel switch transistor 86Similarly, SRAM configuration cell 88 drives n-channel switch transistor90; and SRAM configuration cell 92 drives n-channel switch transistor86. The n-channel switch transistors 86, 90, and 94 connect circuit netstogether and need to be overdriven to prevent a V_(t) drop in the signalpath. Consequently, the use of the SRAM configuration cell 10 of FIG. 3is preferred to provide overdrive to the gates of the switch transistors86, 90, and 94.

While embodiments and applications of this invention have been shown anddescribed, it would be apparent to those skilled in the art that manymore modifications than mentioned above are possible without departingfrom the inventive concepts herein. The invention, therefore, is not tobe restricted except in the spirit of the appended claims.

What is claimed is:
 1. A random-access memory cell comprising: first and second voltage supply nodes; first and second complementary output nodes; first and second complementary bit lines associated with the memory cell; a word line associated with the memory cell; a first pair of series-connected p-channel hybrid FinFET transistors connected between the first power supply node and the first output node; a first pair of series-connected n-channel hybrid FinFET transistors connected between the first output node and the second power supply node; a second pair of series-connected p-channel hybrid FinFET transistors connected between the first power supply node and the first output node; a second pair of series-connected n-channel hybrid FinFET transistors connected between the first output node and the second power supply node; gates of the first pair of series-connected p-channel hybrid FinFET transistors and the first pair of series-connected n-channel hybrid FinFET transistors connected to the second output node; gates of the second pair of series-connected p-channel hybrid FinFET transistors and the second pair of series-connected n-channel hybrid FinFET transistors connected to the first output node; the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
 2. The random-access memory cell of claim 1 wherein: the first bit line is coupled to the first output node through a first n-channel FinFET select transistor; and the second bit line coupled to the second output node through a second re -channel hybrid FinFET select transistor.
 3. The static random-access memory cell of claim 1 further comprising control circuitry configured to supply a programming potential to the first voltage supply node during a programming mode and supply an operating potential higher than the programming potential during a read mode.
 4. The static random-access memory cell of claim 1 further comprising an re -channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes.
 5. A static random-access memory cell comprising: first and second voltage supply nodes; first and second complementary output nodes; first and second complementary bit lines associated with the memory cell; a word line associated with the memory cell; a first pair of series-connected p-channel hybrid FinFET transistors connected between the first voltage supply node and the first output node; a first pair of series-connected n-channel hybrid FinFET transistors connected between the second voltage supply node and the first output node; a second pair of series-connected p-channel hybrid FinFET transistors connected between the first voltage supply node and the second output node; a second pair of series-connected n-channel hybrid FinFET transistors connected between the second voltage supply node and the second output node; the first pair of series-connected p-channel hybrid FinFET transistors and the first pair of series-connected n-channel hybrid FinFET transistors each having gates connected together to the second output node, and the second pair of series-connected p -channel hybrid FinFET transistors and the second pair of series-connected n-channel hybrid FinFET transistors each having gates connected together to the second output node; an n-channel hybrid FinFET transistor switch having a gate connected to one of the first and second output nodes; a first n-channel hybrid FinFET select transistor coupled between the first bit line and the first output node; a second n-channel hybrid FinFET select transistor coupled between the second bit line and the second output node; and the first and second n-channel hybrid FinFET select transistors each having a gate coupled to the word line.
 6. The static random-access memory cell of claim 5 further comprising control circuitry configured to supply a programming potential to the first voltage supply node during a programming mode and supply an operating potential higher than the programming potential during a read mode.
 7. The static random-access memory cell of claim 5 further comprising an re -channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes.
 8. A method of operating a random-access memory cell formed from pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors coupled to a pair of complementary bit lines through a pair of hybrid FinFET select transistors, the method comprising: during a programming mode of operation powering the memory cell with a first voltage potential and placing one of the first potential and 0V on a first one of the bit lines and the other one of the first potential and 0V on a second one of the bit lines; and during a read mode of operation powering the memory cell with a second voltage potential higher than the first voltage potential and placing half of the second voltage potential on both of the complementary bit lines.
 9. The method of claim 8 further comprising: during the programming mode of operation selecting the memory cell for programming by placing the first voltage potential on gates of the pair of hybrid FinFET select transistors or deselecting the memory cell for programming by placing 0V on the gates of the pair of hybrid FinFET select transistors.
 10. An integrated circuit comprising: a plurality of first random-access memory cells each including first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with each first memory cell, and a word line associated with each first memory cell, each first memory cell further including pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node; and a plurality of second random-access memory cells each including first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with each second memory cell, and a word line associated with each second memory cell, each second memory cell further including cross-coupled p-channel and n-channel hybrid FinFET transistors connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
 11. The integrated circuit of claim 10, wherein: the first random-access memory cells each further comprise an n-channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes; and the second random-access memory cells each further comprise an n-channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes.
 12. The integrated circuit of claim 10 further comprising control circuitry configured to supply a programming potential to the first voltage supply node plurality of the first random-access memory cells during a programming mode and supply an operating potential higher than the programming potential of the plurality of first random -access memory cells during a read mode. 